In the prior art, the discrete cosine transformation (DCT) operation circuit is equipped with a plurality of multipliers for multiplying input data and DCT transformation coefficients.
In the case of a DCT matrix operation composed of 8 rows and 8 columns (8.times.8), as generally used in the JPEG system or the MPEG system, for example, there are provided eight multipliers.
However, the multiplier is equipped with a number of gates to raise a drawback that the gate scale of the entire operation circuit is enlarged. In addition, the operating frequency of the multipliers is equal to the frequency (which is equal to the frequency of the inputting timing of the input data) of the outputting timing of the DCT operation result, and the product of their ratio (i.e., "1") and the number of multipliers is as large as "8" to raise another drawback that the power consumption is increased. Specifically, the multipliers are driven with a high operating frequency, so that they consume a high power when driven. The number of the multipliers is as large as eight in the prior art so that the power consumption is further increased.
As a measure for improvement, there is disclosed in Japanese Patent Laid-Open No. 4-280368, a DCT operation circuit which is constructed by using two multipliers operated with a frequency four times as high as that of the inputting timing of the data inputted to the DCT operation circuit. In this DCT operation circuit, for example, an input data x.sub.11 is multiplied by DCT transformation coefficients d.sub.11, d.sub.21, d.sub.31 and d.sub.41 by one multiplier, and by DCT transformation coefficients d.sub.51, d.sub.61, d.sub.71 and d.sub.81 by the other multiplier, thereby obtaining four multiplication results x.sub.11 d.sub.11, x.sub.11 d.sub.21, x.sub.11 d.sub.31 and x.sub.11 d.sub.41, and four multiplication results x.sub.11 d.sub.51, x.sub.11 d.sub.61, x.sub.11 d.sub.71 and x.sub.11 d.sub.81. The eight multiplication results thus obtained are stored in eight registers.
Another input data x.sub.21 is also multiplied by DCT transformation coefficients d.sub.12, d.sub.22, d.sub.32 and d.sub.42 by one multiplier and by DCT transformation coefficients d.sub.52, d.sub.62, d.sub.72 and d.sub.82 by the other multiplier, thereby obtaining four multiplication results x.sub.21 d.sub.22, x.sub.21 d.sub.22, x.sub.21 d.sub.32 and x.sub.21 d.sub.42, and four multiplication results x.sub.21 d.sub.52, x.sub.21 d.sub.62, x.sub.21 d.sub.72 and x.sub.21 d.sub.82. The eight multiplication results thus obtained are stored in eight registers. Moreover, the eight multiplication results x.sub.21 d.sub.12, x.sub.21 d.sub.22, x.sub.21 d.sub.32, x.sub.21 d.sub.42, x.sub.21 d.sub.52, x.sub.21 d.sub.62, x.sub.21 d.sub.72 and x.sub.21 d.sub.82 and the preceding eight multiplication results x.sub.11 d.sub.11, x.sub.11 d.sub.21, x.sub.11 d.sub.31, x.sub.11 d.sub.41, x.sub.11 d.sub.51, x.sub.11 d.sub.61, x.sub.11 d.sub.71 and x.sub.11 d.sub.81 read out from the foregoing eight registers are added by adders, and the addition results are stored again in the aforementioned eight registers.
By repeating the operation composed of such multiplication and cumulative addition eight times, the elements y.sub.11 to y.sub.81 of the matrix are determined. By repeating the operation eight times, moreover, all the elements of the matrix are determined. Thus, the one-dimensional 8.times.8 DCT matrix operation is ended.
In the DCT operation circuit disclosed in Japanese Patent Laid-Open No. 4-280368, however, two multipliers are used and therefor improvement in the circuit scale is still needed. In other words, the number of multipliers is desirably reduced to one so that the circuit scale may be minimized.
In the DCT operation circuit of the aforementioned Laid-Open, moreover, the multipliers are operated with a frequency four times as high as that of the inputting timing of the data inputted to the DCT operation circuit. As a result, the product of the ratio (hereinafter referred to as the "normalized frequency") of the operating frequency of the multipliers to the frequency of the inputting timing of the data and the number of multipliers is "8", and no improvement has been made in the power consumption. In order to reduce the power consumption, the product of the normalized frequency and the number of multipliers is desired to be minimized as much as possible.
The invention has been made in view of the circumstances and has a main object to provide a discrete cosine transformation operation circuit whose power consumption is reduced by setting the product of the number of multipliers of a one-dimensional discrete cosine transformation operation circuit and the normalized frequency at 4 and to reduce the circuit scale by setting the number of multiplier at 1.
The foregoing and other objects and novel features of the invention will become apparent from the following description to be made with reference to the accompanying drawings.